QSFPDD 200G PSM8 10km Optical Transceiver (MPO16)

QSFPDD 200G PSM8 10km Optical Transceiver(MPO16)

RQD-200G-16P8-10

Features

• 8 channels full-duplex transceiver modules
• Supports 8×25Gb/s aggregate bit rates
• Supports 8×10Gb/s aggregate bit rates if required
• 8 channels 1310nm DFB
• 8 channels PIN photo detector array
• Internal CDR circuits on both receiver and transmitter channels
• Support CDR bypass
• Low power consumption <6.5W
• Hot Pluggable QSFP DD form factor
• Up to 10km reach for G.652 SMF
• Single male MPO16(APC 8-degree) connector receptacle
• Operating case temperature 0°C to +70°C
• 3.3V power supply voltage
• RoHS compliant (lead free)

Applications

• 2×100G Ethernet links
• Infiniband DDR/EDR
• Datacenter and Enterprise networking

Figure 1. Module Block Diagram

The 200G QSFP DD PSM8 is one kind of parallel transceiver. DFB and PIN array package is key technique, through I2C system can contact with module.

Absolute Maximum Ratings

Recommended Operating Conditions

Electrical Specifications

Note:

1. Differential input voltage amplitude is measured between TxnP and TxnN.

2. Differential output voltage amplitude is measured between RxnP and RxnN.

Optical Characteristics 

Note:

1. Even if the TDP<1dB,the OMA min must exceed the minimum value specified here.

2. The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical inputsignal having this power level on one lane. The receiver does not have to operate correctly at this input power.

3. Sensitivity is specified at 5E-5 BER at 25.78125Gb/s.

4. Sensitivity is specified at 1E-12 BER at 10.3125Gb/s.

Pin Description

Figure 2. Electrical Pin-out Details

ModSelL Pin

The ModSelL is an input signal that must be pulled to Vcc in the QSFP-DD module. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple QSFP-DD modules on a single 2-wire interface bus. When ModSelL is “High”, the module shall not respond to or acknowledge any 2-wire interface communication from the host.

In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the ModSelL de-assert time after any QSFP-DD modules are deselected. Similarly, the host must wait at least for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and de-asserting periods of different modules may overlap as long as the above timing requirements are met.

ResetL Pin

The ResetL signal shall be pulled to Vcc in the module. A low level on the ResetL signal for longer than the minimum pulse length (t_Reset_init) (See  Table 13 ) initiates a complete module reset, returning all user module settings to their default state.

InitMode Pin

InitMode is an input signal. The InitMode signal must be pulled up to Vcc in the QSFP-DD module. The InitMode signal allows the host to define whether the QSFP-DD module will initialize under host software control (InitMode asserted High) or module hardware control (InitMode deasserted Low). Under host software control, the module shall remain in Low Power Mode until software enables the transition to High Power Mode, as defined in Section 7.5. Under hardware control (InitMode de-asserted Low), the module may immediately transition to High Power Mode after the management interface is initialized. The host shall not change the state of this signal while the module is present. In legacy QSFP applications, this signal is named LPMode. See SFF-8679 for signal description.

ModPrsL Pin

ModPrsL must be pulled up to Vcc Host on the host board and grounded in the module. The ModPrsL is asserted “Low” when the module is inserted and deasserted “High” when the module is physically absent from the host connector.

IntL Pin

IntL is an output signal. The IntL signal is an open collector output and must be pulled to Vcc Host on the host board. When the IntL signal is asserted Low it indicates a change in module state, a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL signal is deasserted “High” after all set interrupt flags are read.

Power Supply Filtering

The host board should use the power supply filtering shown in Figure 3.

Figure 3. Host Board Power Supply Filtering

Optical Interface Lanes and Assignment

The optical interface port is a male MPO16 connector . 

Figure 4. Optical Receptacle and Channel Orientation

DIAGNOSTIC MONITORING INTERFACE

Digital diagnostics monitoring function is available on all FiberWDM QSFP DD products. A 2-wire serial interfaceprovides user to contact with module.

The structure of the memory is shown in Figure 5. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed.

The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to enable a one-time-read for all data related to an interrupt situation. After an interrupt, IntL, has been asserted,the host can read out the flag field to determine the affected channel and type of flag.