QSFPDD 200G 2xCWDM4 2km Optical Transceiver

RQD-200G-2CWDM4

Features

• 8 channels full-duplex transceiver modules
• Supports 8×25Gb/s aggregate bit rates
• Supports 8×10Gb/s aggregate bit rates if required
• 8 channels DFB with 2xCWDM4 wavelength
• 8 channels PIN photo detector
• Internal CDR circuits on both receiver and transmitter channels
• Support CDR bypass
• Low power consumption <6.5W
• Hot pluggable QSFP DD form factor
• Up to 2km reach for G.652 SMF
• Dual Duplex LC receptacles
• Operating case temperature 0°C to +70°C
• 3.3V power supply voltage
• RoHS compliant (lead free)

Applications

• 200GBASE 2 x CWDM4 Ethernet
• Data Center Network

Description

FiberWDM’s RQD-200G-2CWDM4 200GE QSFP-DD 2xCWDM4 Optical Transceiver modules are designed for using in 2x100G Ethernet 2km links over single-mode fiber. They are compliant with the QSFP-DD MSA and with CWDM4 MSA. Digital diagnostics functions are available via the I2C interface as specified by CMIS V4.0. These modules can convert 8 channels of 25Gbps NRZ electrical input data to 8 channels of 25Gbps NRZ optical signal (2xCWDM4), and also can convert 8 channels of 25Gbps NRZ optical signal (2xCWDM4) to 8 channels of 25Gbps NRZ electrical output data. And these modules incorporate FiberWDM Technologies proven circuit to provide reliable long life, high performance, and consistent service.

Figure1. Module Block Diagram

Absolute Maximum Ratings

Recommended Operating Conditions

Electrical Specifications

Note：

Note1. Differential input voltage amplitude is measured between TxnP and TxnN.

Note2. Differential output voltage amplitude is measured between RxnP and RxnN.

Optical Characteristics 

Table 3 - Optical Characteristics

Note：

Note3. Receiver sensitivity (OMA), each lane (max) at 5 x 10-5 BER is a normative specification.

Pin Description

ModSelL Pin

The ModSelL is an input signal that shall be pulled to Vcc in the QSFP-DD module. When held low by the host, the module responds to 2-wire serial communication commands. The ModSelL allows the use of multiple QSFP-DD modules on a single 2-wire interface bus. When ModSelL is “High”, the module shall not respond to or acknowledge any 2-wire interface communication from the host.

In order to avoid conflicts, the host system shall not attempt 2-wire interface communications within the ModSelL de-assert time after any QSFP-DD modules are deselected. Similarly, the host must wait at least for the period of the ModSelL assert time before communicating with the newly selected module. The assertion and de-asserting periods of different modules may overlap as long as the above timing requirements are met.

ResetL Pin

The ResetL signal shall be pulled to Vcc in the module. A low level on the ResetL signal for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state.

LPMode Pin

LPMode is an input signal. The LPMode signal shall be pulled up to Vcc in the QSFP-DD module. LPMode is used in the control of the module power mode. See CMIS Section 6.3.1.3.

ModPrsL Pin

ModPrsL shall be pulled up to Vcc Host on the host board and pulled low in the module. The ModPrsL is asserted “Low” when the module is inserted. The ModPrsL is deasserted “High” when the module is physically absent from the host connector due to the pull-up resistor on the host board.

IntL Pin

IntL is an output signal. The IntL signal is an open collector output and shall be pulled to Vcc Host on the host board. When the IntL signal is asserted Low it indicates a change in module state, a possible module operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL signal is deasserted “High” after all set interrupt flags are read.

Power Supply Filtering

The host board should use the power supply filtering shown in Figure3.

Figure3. Host Board Power Supply Filtering

Optical Interface Lanes and Assignment

The optical interface port is Dual Duplex LC connector.

Figure 4. Optical Receptacle

DIAGNOSTIC MONITORING INTERFACE

Digital diagnostics monitoring function is available on all FiberWDM QSFP DD products. A 2-wire serial interface is provided for user to contact with module.

Memory Structure and Mapping

Due to eight-bit addresses limited, the management memory that can be directly accessed by the host to 256 bytes, which is divided in Lower Memory (addresses 00h through 7Fh) and Upper Memory (addresses 80h through FFh).

A larger addressable management memory is required for all but the most basic modules. This is supported by a structure of 128-byte pages, together with a mechanism for dynamically mapping any of the 128-byte pages from a larger internal management memory space into Upper Memory the host addressable space.

The addressing structure of the additional internal management memory is shown in Figure 5. The management memory inside the module is arranged as a unique and always host accessible address space of 128 bytes (Lower Memory) and as multiple upper address subspaces of 128 bytes each (Pages), only one of which is selected as host visible in Upper Memory. A second level of Page selection is possible for Pages for which several instances exist (e.g. where a bank of pages with the same Page number exists).

This structure supports a flat 256 byte memory for passive copper modules and permits timely access to addresses in the Lower Memory, e.g. Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function in the Lower Page. For more complex modules which require a larger amount of management memory the host needs to use dynamic mapping of the various Pages into the host addressable Upper Memory address space, whenever needed.

Note: The management memory map has been designed largely after the QSFP memory map. This memory map has been changed in order to accommodate 8 electrical lanes and to limit the required memory space. The single address approach is used as found in QSFP. Paging is used in order to enable time critical interactions between host and module.

Supported Pages

A basic 256 byte subset of the Management Memory Map is mandatory for all CMIS compliant devices. Other parts are only available for paged memory modules, or when advertised by the module. See CMIS V4.0 for details regarding the advertisement of supported management memory spaces.

In particular, support of the Lower Memory and of Page 00h is required for all modules, including passive copper cables. These pages are therefore always implemented. Additional support for Pages 01h, 02h and bank 0 of Pages 10h and 11h is required for all paged memory modules.

Bank 0 of pages 10h-1Fh, provides lane-specific registers for the first 8 lanes, and each additional bank provides support for additional 8 lanes. Note, however, that the allocation of information over the banks may be page specific and may not to be related to grouping data for 8 lanes.

The structure allows address space expansion for certain types of modules by allocating additional Pages. Moreover, additional banks of pages.

Figure5. QSFP DD Memory Map

Mechanical Dimensions

Figure6. Mechanical Specifications

Regulatory Compliance

FiberWDM RQD-200G-2CWDM4 transceivers are Class 1 Laser Products. They are certified per the following standards:

References

1. QSFPDD MSA

2. CMIS4.0

3. CWDM4 MSA

4. Directive 2011/65/EU of the European Parliament and of the Council, “on the restriction of the use of certain hazardous substances in electrical and electronic equipment,” July 1, 2011.

CAUTION: 

Use of controls or adjustment or performance of procedures other than those specified herein may result in hazardous radiation exposure.

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